/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright(c) 2021 Ramaxel Memory Technology, Ltd */

#ifndef SPHW_COMMON_CMD_H
#define SPHW_COMMON_CMD_H

/* COMM Commands between Driver to MPU */
enum sphw_mgmt_cmd {
	COMM_MGMT_CMD_FUNC_RESET = 0,
	COMM_MGMT_CMD_FEATURE_NEGO,
	COMM_MGMT_CMD_FLUSH_DOORBELL,
	COMM_MGMT_CMD_START_FLUSH,
	COMM_MGMT_CMD_SET_FUNC_FLR,
	COMM_MGMT_CMD_GET_GLOBAL_ATTR,

	COMM_MGMT_CMD_SET_CMDQ_CTXT = 20,
	COMM_MGMT_CMD_SET_VAT,
	COMM_MGMT_CMD_CFG_PAGESIZE,
	COMM_MGMT_CMD_CFG_MSIX_CTRL_REG,
	COMM_MGMT_CMD_SET_CEQ_CTRL_REG,
	COMM_MGMT_CMD_SET_DMA_ATTR,

	COMM_MGMT_CMD_GET_MQM_FIX_INFO = 40,
	COMM_MGMT_CMD_SET_MQM_CFG_INFO,
	COMM_MGMT_CMD_SET_MQM_SRCH_GPA,
	COMM_MGMT_CMD_SET_PPF_TMR,
	COMM_MGMT_CMD_SET_PPF_HT_GPA,
	COMM_MGMT_CMD_SET_FUNC_TMR_BITMAT,

	COMM_MGMT_CMD_GET_FW_VERSION = 60,
	COMM_MGMT_CMD_GET_BOARD_INFO,
	COMM_MGMT_CMD_SYNC_TIME,
	COMM_MGMT_CMD_GET_HW_PF_INFOS,
	COMM_MGMT_CMD_SEND_BDF_INFO,
	COMM_MGMT_CMD_GET_VIRTIO_BDF_INFO,

	COMM_MGMT_CMD_UPDATE_FW = 80,
	COMM_MGMT_CMD_ACTIVE_FW,
	COMM_MGMT_CMD_HOT_ACTIVE_FW,
	COMM_MGMT_CMD_HOT_ACTIVE_DONE_NOTICE,
	COMM_MGMT_CMD_SWITCH_CFG,
	COMM_MGMT_CMD_CHECK_FLASH,
	COMM_MGMT_CMD_CHECK_FLASH_RW,
	COMM_MGMT_CMD_RESOURCE_CFG,

	COMM_MGMT_CMD_FAULT_REPORT = 100,
	COMM_MGMT_CMD_WATCHDOG_INFO,
	COMM_MGMT_CMD_MGMT_RESET,
	COMM_MGMT_CMD_FFM_SET,

	COMM_MGMT_CMD_GET_LOG = 120,
	COMM_MGMT_CMD_TEMP_OP,
	COMM_MGMT_CMD_EN_AUTO_RST_CHIP,
	COMM_MGMT_CMD_CFG_REG,
	COMM_MGMT_CMD_GET_CHIP_ID,
	COMM_MGMT_CMD_SYSINFO_DFX,
	COMM_MGMT_CMD_PCIE_DFX_NTC,
};

#endif /* SPHW_COMMON_CMD_H */
